1. Field of the Invention
The present invention disclosed in the present specification relates to a semiconductor device having an SOI (Silicon-On-Insulator) structure and more particularly to a structure of an insulated gate field effect transistor having the SOI structure (called as an SOI-MOSFET or an SOI-IGFET).
The technology of the present invention exhibits its effect in fabricating a submicron device whose channel length or channel width is less than 1 .mu.m (typically 30 to 500 nm).
The present invention is applicable to various semiconductor integrated circuits such as IC, VLSI and ULSI constructed by integrating the MOSFETs having the SOI structure (hereinafter referred to as an SOIFET).
2. Description of Related Art
An SOIFET is now attracting attention as a semiconductor device replacing a MOSFET using bulk mono-crystal silicon. The SOIFET is characterized in that it is advantageous over the MOSFET in terms of high-speed operability and lower power consumption.
Then, while the research and development on VLSI, ULSI and the like using the SOIFET are actively conducted, there is a steady tendency of sub-micronizing the device size to enhance the integration of integrated circuits.
As for a channel length (L), it has now come to be required a work size in a deep sub-micron range of less than 0.2 .mu.m or 0.1 .mu.m. Similarly to that, a work size of less than 0.2 .mu.m is required for a gate width (W) and a device size of L:W=1:1 has come to be proposed.
In the field of MOSFETs, there has been known a phenomenon called a short-channel effect as a factor of hindering the sub-micronization. The short-channel effect is an effect which causes various problems such as a drop of a withstand voltage between a source and a drain and a drop of a threshold voltage when the channel length is shortened (see "Submicron Device I" Mitsumasa Koyanagi and others, pp. 88 through 138, Maruzen Co., Ltd.).
According to the reference book, a punch-through phenomenon is known the most as one of causes of the drop of the withstand voltage. This phenomenon makes it difficult to control carriers by gate voltage as a potential influence of a depletion layer on the drain side extends to the source side and a diffusion potential of the source side is lowered when the channel length is shortened (drain-inducted barrier lowering phenomenon).
Such short-channel effect poses a similar problem also in the SOIFET, which must be overcome in forwarding the sub-micronization. Here, a mechanism how the short-channel effect occurs in the SOIFET (partial depletion type) will be explained with reference to schematic diagrams of FIGS. 3A through 3C.
As shown in FIG. 3A, the SOIFET comprises a mono-crystal silicon substrate 301, a buried oxide film 302, a field oxide film 303 for insulating a mono-crystal silicon layer on the oxide film 302, a source region 304, a drain region 305 and a channel forming region 306. The source and drain regions are formed by doping an impurity element to the mono-crystal silicon layer. The SOIFET further comprises a gate insulating film 307 and a gate electrode 308.
FIG. 3B is a schematic diagram drawn focusing on the channel forming region 306 in FIG. 3A. It is noted that the hatched portion 309 in FIG. 3B is a depletion layer spreading within the channel forming region.
Normally (when a channel length L is long), a depletion layer having an equal depth is formed under the channel formed right under the gate electrode 308. However, when the channel length (L) is shortened to the extreme, the depletion layer extended from the drain side spreads in the direction of the source region and contacts with the depletion layer of the source side in the end (FIG. 3B).
As a result, a potential barrier in the vicinity of the source is lowered by the drain voltage and a current flows by itself even when no voltage is applied to the gate electrode. In this case, an energy band between the source and the drain changes continuously as shown in FIG. 3C. This is the punch-through effect which lowers the withstand voltage between the source and the drain.
While various countermeasures have been taken to the short-channel effect described above, a measure which has been taken most in general is channel-doping. The channel-doping is a technique for suppressing the short-channel effect by doping a trace amount of impurity element such as P (phosphorus) and B (boron) shallowly over the whole channel forming region (as disclosed in Japanese Patent Laid Open Nos. Hei. 4-206971, 4-286339 and others).
However, the channel-doping technique has a drawback that it restricts the field effect mobility (hereinafter referred to simply as a mobility) of the MOSFET significantly. That is, the move of carriers is hampered by the impurity intentionally doped, thus dropping the mobility.
Further, there has been known a substrate floating effect (called also as a kink phenomenon) caused by impact ionization of implanted carriers as a cause of the drop of the withstand voltage between the source and the drain in the SOI structure. This will be explained below by exemplifying an N-channel type SOIFET.
Electrons (major carriers) which have been attracted by a strong electric field and put into the high energy state in the vicinity of the drain collide with silicon lattice and generate a large amount of pairs of electron and positive hole (impact ionization phenomenon). The positive holes (minority carriers) generated at this time are pushed back by the drain electric field and are accumulated under the channel.
The positive holes accumulated under the channel boost the potential in the channel part, so that the source, the channel and the drain turn out to be an emitter, a base and a collector, respectively, thus turning on a parasitic bipolar transistor.
Thus, a through current flows between the source and the drain, causing a breakdown phenomenon of the withstand voltage between the source and the drain. While such phenomenon has been known also in the MOSFET using the bulk mono-crystal as a carrier implantation induced breakdown phenomenon, it poses a more serious problem in the SOI structure in which the substrate potential is floating.